1. Field of the Invention
The disclosed embodiments relate to stacked chip modules and, more particularly, to a stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks that allow for servicing (e.g., self-testing or self-repairing) of functional blocks (e.g., memory arrays) at both the wafer-level and stacked chip module-level.
2. Description of the Related Art
When individual integrated circuit (IC) chips are mounted side-by-side on a printed circuit board (PCB), they take up a significant amount of surface area. Additionally, signals are typically passed from chip to chip on the PCB through large high-power, high-speed links. Recently developed stacked chip modules (also referred to herein as stacked chip packages, three-dimensional (3D) chip stacks or 3D multi-chip modules) allow for reductions in form factor, interface latency and power consumption as well as an increase in bandwidth. These benefits stem from the fact that, within a stacked chip module, signals are passed through the chips using simple wire-based interconnects (e.g., through-substrate-vias (TSVs) and micro-controlled collapsed chip connections (C4-connections)). Thus, there is a reduction in wire delay, which results in corresponding reductions in interface latency and power consumption as well as an increase in bandwidth. Unfortunately, self-maintenance (i.e., self-servicing, such as self-testing and/or self-repairing) of the individual IC chips on a stacked chip module presents a number of special challenges and such self-maintenance is can be critical to ensure product reliability.